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Chapter 5: Using HIL
5–7
Troubleshooting HIL Designs
When you set this option, you can specify the required number of data packets as the
Burst length . The HIL block sends data to the hardware in bursts of the size you
specify.
1
DSP Builder determines the size of the packet by the larger of the total input data
width or the total output data width. If the packet size multiplied by the Burst length
exceeds the preset data array, DSP Builder sets the Burst length to 1.
Simulation using burst mode works the same as single clock mode, but DSP Builder
introduces a latency of the specific packet size on the output signals of the HIL blocks.
As a consequence, feedback-loops may not work properly unless you enclose them in
the HIL block, and some intervention may be necessary when comparing or
visualizing HIL simulation results.
The HIL block uses software buffers to send and receive from the hardware, so you
can change these buffer sizes without recompiling the HIL function.
Troubleshooting HIL Designs
This section describes various issues that you may encounter when you are using HIL
designs.
1
If the top-level of your design changes, compile and reload the Quartus II project into
HIL to ensure that all information is up-to-date.
Fails to Load the Specified Quartus II Project
HIL reads design information, such as clock, reset, and input and output ports, from
the specified Quartus II project. However, it can fail to load your project if the project
is not compiled with the Quartus II Fitter, there is a Quartus II version mismatch, or
the Quartus II project file is not up-to-date.
No Inputs Found From the Quartus II Project
This issue occurs if the DSP Builder model file contains only the internally induced
signals, such as from a counter, and also does not produce any outputs. However, HIL
simulation works correctly.
No Outputs Found From the Quartus II Project
This issue occurs if your design does not have any outputs and makes the HIL
simulation meaningless.
HIL Design Stays in Reset During Simulation
An asynchronous reset is permanently asserted for a HIL design.
Action:
Check that the reset active level matches the setting in the original design. Recompile
the HIL design after you have changed the reset level.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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